![]() ![]() USICR – The control register to define the set up.Īnd there is one more register, the data buffer USIBR.Hence the registers and the operation principle is a bit different to SPI on an ATmega.īesides the data register (called USIDR for USI), there are two more registers: #Attiny usi uart serialThere is a schematic in the ATtiny datashet in the USI section, which describes it very good.Ī specialty of the ATtiny controllers is that they don’t have a dedicated SPI interface but the Universal Serial Interface (USI), which can be configured to use SPI, I2C or UART. So master and slave can send at the same time. Since this data register is 8-bit long, this is also the length of one data frame.ĭue to the two data wires, the communication can be full-duplex. With every clock cycle it shifts bit per bit out the output port (DO) on one side of the register and in from the the input port (DI) on the other side. One shift register stores the received and data to be sent. The data transmission is synchronized by the clock signal between master and slave, so that the signal reading and sending is triggered by the edges of the clock signal.
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